This module handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 100GbE Ethernet PCS and PMA. The Altera 100G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 803.3ba 2010 Higher Speed Ethernet Standard. This system can be represented by the following diagram: f/fa/100G_CAUI_system.jpg TCL based System Controller for configuration and control of the system.Built in Tx to Rx serial loopback function Built in different packet counters including error packet counts System Overview The hardware platform consists of three sub-systems: System console and TCL based flexible, reusable, and extendable user interface allows users to dynamically configure various registers provided by this demo design.32-bit Avalon-MM interface to do register access.

Check for Hardware errors in the MAC & PHY. Compare packet statistics at Transmit and receive MACs. Uses a standard 512-bit Avalon-ST interface to connect to the Ethernet Traffic Generator.Stand-alone and easy-to-use reference design example with flexibility to dynamically select traffic profile.This hardware demonstration reference design offers the following features: This design provides a flexible test and demonstration platform which effectively control, test, and monitor 100Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP module with 10 x 10Gbps full-duplex channels. It is configured to demonstrate on a Stratix V GX 100G Development Board using Altera development tool Quartus II release 15.0. This reference design demonstrates the operation of Altera® 100-Gbps Ethernet MAC and PHY IP solution on a Stratix V GX device (5SGXEA7N2F45C2). 100Gbps Ethernet 10x10 MAC PHY IP CFP Hardware Demo Design Titleġ00G Ethernet 10x10 MAC-PHY IP Hardware demo design on 100G Stratix V GX Development Board Introduction

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